1. Field of Invention
The present invention relates to an OR/NAND circuit. More particularly, the present invention relates to an OR/NAND circuit configured by several magnetic transistors.
2. Description of Related Art
‘OR’ and ‘NAND’ logic circuits are very important for IC circuit design. The designer can combine these two logic circuits with other logic circuits to implement the required functions.
FIG. 1 is a CMOS circuit with the NAND logic function of the prior art. The CMOS circuit has two PMOS transistors 100 and 130 coupled in parallel, and two NMOS transistors 160 and 190 coupled in series. The NMOS transistor 190 couples to the low voltage end 140, and the PMOS transistors 100 and 130 couple to the high voltage end 120. The input signal ‘X’ at the input end 110 controls the PMOS transistor 100 and NMOS transistor 160. The Input signal ‘Y’ at the input end 150 controls the PMOS transistor 130 and NMOS transistor 190. The CMOS circuit generates the NAND logic function (output=(X·Y)′) at the output end 170.
The Giant Magnetoresistance Effect (GMR) is a quantum mechanical effect observed in structures with alternating thin magnetic and thin nonmagnetic sections. The GMR effect shows a significant change in electrical resistance from the zero-field high resistance state to the high-field low resistance state according to an applied external field.
Therefore, the GMR effect can be used to design the magnetic transistor. Thus, magnetic transistors can further be used to integrate a magnetic OR/NAND circuit without the expensive process and equipment. The magnetic OR/NAND circuit can be designed and manufactured with short programming time and high density.
For the foregoing reasons, there is a need to have a magnetic OR/NAND circuit integrated by magnetic transistors.